techni cal data 2011, february, rev. 0 2 dc -to- dc converter control circuits the il34063a is a monolithic control circuit containing the primary functions required for dc - to - dc converters. these devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. this series was specifically designed to be incorporated in step - down and step - up and voltage - inverting applications with a minimum number of external compo nents. features functional block dia gram ? operation from 3.0 v to 40 v input ? low standby current ? current limiting ? output switch current to 1.5 a ? output voltage adjustable ? frequency operation to 100 khz ? precision 2% reference maximum ratings rati ng symbol value unit power supply voltage v cc 40 vdc comparator input voltage range v ir - 0.3 to +40 vdc switch collector voltage v c(switch) 40 vdc switch emitter voltage (vpin 1 = 40 v) v e(switch) 40 vdc switch collector to emitter voltage v ce(switch) 40 vdc driver collector voltage i c(driver) 40 vdc driver collector current (note 1) i c(driver) 100 ma switch current i sw 1.5 a power dissipation and thermal characteristics ceramic package, u suffix t a = +25c thermal resistance plastic package, p s uffix t a = +25c thermal resistance soic package, d suffix ta = +25c thermal resistance p d r ja p d r ja p d r ja 1.25 100 1.25 100 625 160 w c/w w c/w mw c/w operating junction temperature tj +150 c operating ambient temperature range t a 0 to + 70 c storage temperature range tstg - 65to+150 c * stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditions? is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. il34063a
i l 34063 a 2011, february, rev. 0 2 ordering information device temperature range package 34063ad 0 to + 70 c so - 8 34063an plastic dip (v cc = 5.0 v, t a = 0 to + 70 o c unless otherwi se specified.) electrical charactericistics characteristics symbol min typ max unit oscillator frequency (v pin 5 = 0 v, c t = 1.0 nf, t a = 25c) fosc 24 33 42 khz charge current (v cc = 5.0 v to 40 v, t a = 25c) ichg 24 33 42 a discharge current ( v cc = 5.0 v to 40 v, t a = 25c) idi schg 140 200 260 a discharge to charge current ratio (pin7 to vcc, t a =25c) idischg/ichg 5.2 6.2 7.5 ? current limit sense voltage (ichg = idischg, t a = 25c) v i pk(sense) 250 300 350 mv output switch (note 3) saturation voltage, darlington connection (i sw = 1.0 a, pins 1, 8 connected) v ce (sat) ? 1.0 1.3 v saturation voltage (i sw = 1.0 a, r pin 8 = 82 ? to v cc . forced = 20) v ce (sat) ? 0.45 0.7 v dc current gain (i sw = 1.0 a, v ce = 5.0 v, t a = 25c) h fe 50 120 ? ? collector off - state current (v ce = 4 0v) i c (off) ? 0.01 100 a comparator threshold voltage (t a = 25c) (t a = t low to t high ) vth 1.225 1.21 1.25 ? 1.275 1.29 v threshold voltage (t a = 25c) ** vth 1.2375 1.25 1.2625 v threshold voltage line regulation (v cc = 3 0 v to 40 v) reg line 1.4 5.0 mv input bias current (vin=0v) i ib ? - 40 - 400 na total device supply current (v cc = 5 0 v to 40 v, c t = 1 0 nf, v pin7 = v cc . v pin5 > vth, pin 2 = gnd, remaining pins open) i cc 2.5 4.0 ma notes: 1. maximum package power dissipation limits must be observed. 2. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as poss ible 3. if the output switch is driven into hard saturation (non darlington configuration) at low switch currents (< 300 ma) and high driver currents (>30 ma), it may take up to 2.0 s to come out of saturation this condition will shorten the off' time at frequencies > 30 khz, and is magnified at high temperatures this condition does not occur with a darlington confi guration, since the output switch cannot saturate if a non darlington configuration is used, the following output drive condition is recommended forced of output switch = i c , output/(ic, driver - 7.0 ma*) > 10 *the 100 ? . resistor in the emitter of the d river device requires about 7.0 ma before the output switch conducts ** possible version for shipment pin connection
i l 34063 a 2011, february, rev. 0 2 typical application circuit s step - up converter test condition (v out = 28 v) test conditions value (typ) unit line regulation v in = 8 to 16 v, i o = 175 ma 30 mv load regulation v in = 12 v, i o = 75 to 175 ma 10 mv output ripple v in = 12 v, i o = 175 ma 300 mv efficiency v in = 12 v, i o = 175 ma 89 % drc l 1 170 h ipk vcc cll swc swe tc gnd 1 2 3 4 8 7 6 5 r 3 r sg d 1 r 1 r 2 180? 0.22 ? + c 2 100 f 2.2k ? 47k ? c 3 1.5nf v out + c 3 330 f v in 12v 34063a/e byv10-40
i l 34063 a 2011, february, rev. 0 2 step - down converter test condition (v out = 5 v) test conditions value (typ) unit line r egulation v in = 15 to 25 v, i o = 500 ma 5 mv load regulation v in = 25 v, i o = 50 to 500 ma 30 mv output ripple v in = 25 v, i o = 500 ma 100 mv efficiency v in = 25 v, i o = 500 ma 80 % i sc v in = 25 v, r load = 0.1 ? 1.2 a drc ipk vcc cll swc swe tc gnd 1 2 3 4 8 7 6 5 34063a/e r sc 0.33 ? + c 2 100 f r 1 r 2 1.2k ? 3.6k ? + c 1 470 f c 3 470pf l 1 220 h d 1 byv10-40
i l 34063 a 2011, february, rev. 0 2 voltage inverting converter test condition (v out = - 12 v) test conditions value (typ) unit line regulation v in = 4.5 to 6 v, i o = 100 ma 15 mv load regulation v in = 5 v, i o = 10 to 100 ma 20 mv output ripple v in = 5 v, i o = 100 ma 230 mv efficiency v in = 5 v, i o = 100 ma 58 % i sc v in = 5 v, r load = 0.1 ? 0.9 a drc ipk vcc cll swc swe tc gnd 1 2 3 4 8 7 6 5 r 3 0.22 ? v in 4.5 to 6v + c 2 100 f r 2 r 1 8.2k ? 953 ? + c 1 1000 f c3 1.5nf d 1 byv10-40 l 1 90 h 34063a/e v out -12v / 100ma
i l 34063 a 2011, february, rev. 0 2 calculation parameter step - up (discontinuous mode) step - down (continuous mode) voltage inverting (discontinuous mode) t on /t off v out +v f - v in(min) v out +v f ? v out ? + v f v in(min) - v sat v in(min) - v sat - v out v in - v sat (t on + t off )max 1/f min 1/f min 1/f min c t 4.5x10 - 5 t on 4.5x10 - 5 t on 4.5x10 - 5 t on i pk(switch) 2i out(max) [ (t on /t off )+1 ] 2i out(max) 2i out(max) [ (t on /t off )+1 ] r sc 0.3/i pk(switch) 0.3/i pk(switch) 0.3/i pk(switch) c o i out t on i pk(switch) (t on + t off ) i out t on v ripple(p - p) 8v ripple(p - p) v ripple(p - p) l(min) v in(min) - v sat t on(max) v in(min) - v sat - v out t on(max) v in(min) - v sat t on(max) i pk(switch) i pk(switch) i pk(switch) notes: v sat = saturation voltage of the output switch v f = forward voltage drop of the output rectifier the following power supply characteristics must be chosen: v in = nominal input voltage v out = desired output voltage, ? v out ? = 1.25(1+r 2 /r 1 ) i out = desired output current fmin = minimum desired output swi tching frequency at the selected values of vin and lo v ripple = desired peak to peak output ripple voltage. in practice, the calculated capacitor value will and to be increased due to its equivalent series resistance and board layout. the ripple voltage sh ould be kept to a low value since it will directly affect the line and load regulation. step - up with external npn switch v out + r sc v in s r q q1 ipk oscillator 1.25v reference regulator - + comparator 8 1 2 3 4 5 6 7
i l 34063 a 2011, february, rev. 0 2 step - down with external npn switch 7 6 5 1 2 3 4 s r q q2 q1 ipk oscillator 1.25 v reforence regulator comparator 8 v in r sc v out + step - down with external pnp swi tch 7 6 5 1 2 3 4 s r q q2 q1 ipk oscillator 1.25 v reference regulator comparator 8 v in r sc v out +
i l 34063 a 2011, february, rev. 0 2 voltage inverting with external npn switch 7 6 5 1 2 3 4 s r q q2 q1 ipk oscillator 1.25 v reference regulator comparator 8 v in r sc v out + voltage inverting with external pnp saturated switch 7 6 5 1 2 3 4 s r q q2 q1 ipk oscillator 1.25 v reforence regulator comparator 8 v in r sc v out +
i l 34063 a 2011, february, rev. 0 2 dual output voltage 7 6 5 1 2 3 4 s r q q2 q1 ipk oscillator 1.25 v reforence regulator comparator 8 v in r sc + + +12v gnd -12v higher output power, higher input voltage 7 6 5 1 2 3 4 s r q q2 q1 ipk oscillator 1.25 v reforence regulator comparator 8 r sc + +v out -v out isolated from input + + - v in
i l 34063 a 2011, february, rev. 0 2 n suffix plastic dip (ms ? 001ba) symbol min max a 8.51 10.16 b 6.1 7.11 c 5.33 d 0.36 0.56 f 1.14 1.78 g h j 0 10 k 2.92 3.81 no tes : l 7.62 8.26 1. dimensions ?a?, ?b? do not include mold flash or protrusions. m 0.2 0.36 maximum mold flash or protrusions 0.25 mm (0.010) per side. n 0.38 d s uffix s oic (ms - 012aa) symbol min max a 4.8 5 b 3.8 4 c 1.35 1.75 d 0.33 0.51 f 0.4 1.27 g h j 0 8 no tes : k 0.1 0.25 1. dimensions a and b do not include mold flash or protrusion. m 0.19 0.25 2. maximum mold flash or protrusion 0.15 mm (0.006) per side p 5.8 6.2 for a; for b ? 0.25 mm (0.010) per s ide. r 0.25 0.5 1.27 5.72 dimens ion, mm dimens ion, mm 2.54 7.62 a b h c k c m j f m p g d r x 45 seating plane 0.25 (0.010) m t -t- 1 8 4 5 l h m j a b f g d se ati ng plane n k 0.25 (0.010) m t -t- c 1 8 4 5
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